Table k=3 t=3 m=5
v,k,t,m	B	Combs	Author	Date	note	Lower Bound
6,3,3,5	2		Trivial (2 blocks)	7-lug-2017		2
7,3,3,5	5	Invers(07,04,02)				5
8,3,3,5	8	Invers(08,05,03)				8
9,3,3,5	12	Invers(09,06,04)				12
10,3,3,5	20	Invers(10,07,05)				20
11,3,3,5	29	Invers(11,08,06)				29
12,3,3,5	40	Invers(12,09,07)				40
13,3,3,5	52	Invers(13,10,08)				52
14,3,3,5	70		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	67
15,3,3,5	89	see WeEf's website				84
16,3,3,5	112		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	104
17,3,3,5	136	see WeEf's website				127
18,3,3,5	168		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	153
19,3,3,5	200	see WeEf's website				182
20,3,3,5	240		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	215
21,3,3,5	280	see WeEf's website				251
22,3,3,5	330		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	291
23,3,3,5	380	see WeEf's website				335
24,3,3,5	440		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	383
25,3,3,5	506		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	436
26,3,3,5	572		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	493
27,3,3,5	650		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	555
28,3,3,5	728		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	622
29,3,3,5	819		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	694
30,3,3,5	910		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	772
31,3,3,5	1015		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	855
32,3,3,5	1120		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	944
33,3,3,5	1240		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	1039
34,3,3,5	1360		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	1140
35,3,3,5	1496		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	1247
36,3,3,5	1632		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	1361
37,3,3,5	1785		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	1482
38,3,3,5	1938		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	1610
39,3,3,5	2109		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	1745
40,3,3,5	2280		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	1887
41,3,3,5	2470		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	2036
42,3,3,5	2660		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	2193
43,3,3,5	2870		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	2358
44,3,3,5	3080		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	2531
45,3,3,5	3311		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	2712
46,3,3,5	3542		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	2902
47,3,3,5	3795		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	3100
48,3,3,5	4048		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	3307
49,3,3,5	4324		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	3523
50,3,3,5	4600		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	3748
51,3,3,5	4900		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	3983
52,3,3,5	5200		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	4227
53,3,3,5	5525		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	4481
54,3,3,5	5850		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	4745
55,3,3,5	6201		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	5019
56,3,3,5	6552		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	5304
57,3,3,5	6930		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	5599
58,3,3,5	7308		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	5905
59,3,3,5	7714		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	6222
60,3,3,5	8120		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	6550
61,3,3,5	8555		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	6889
62,3,3,5	8990		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	7240
63,3,3,5	9455		already known design - Rebuilt by LDDr	1-lug-2018	Sum (v1+v2,k,t,m1+m2-1)	7602
64,3,3,5	9920		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	7976
65,3,3,5	10416		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	8362
66,3,3,5	10912		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	8761
67,3,3,5	11440		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	9172
68,3,3,5	11968		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	9596
69,3,3,5	12529		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	10033
70,3,3,5	13090		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	10483
71,3,3,5	13685		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	10946
72,3,3,5	14280		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	11422
73,3,3,5	14910		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	11912
74,3,3,5	15540		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	12416
75,3,3,5	16206		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	12934
76,3,3,5	16872		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	13466
77,3,3,5	17575		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	14012
78,3,3,5	18278		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	14573
79,3,3,5	19019		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	15149
80,3,3,5	19760		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	15740
81,3,3,5	20540		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	16346
82,3,3,5	21320		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	16967
83,3,3,5	22140		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	17604
84,3,3,5	22960		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	18256
85,3,3,5	23821		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	18924
86,3,3,5	24682		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	19608
87,3,3,5	25585		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	20309
88,3,3,5	26488		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	21026
89,3,3,5	27434		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	21760
90,3,3,5	28380		already known design - Rebuilt by LDDr	9-giu-2018	Sum (v1+v2,k,t,m1+m2-1)	22511