Table k=6 t=2 m=4 |
v,k,t,m | B | Combs | Author | Date | note | Lower Bound |
7,6,2,4 |
1 | | Trivial (1 block) | 7-lug-2017 | | 1 |
8,6,2,4 |
1 | | Trivial (1 block) | 7-lug-2017 | | 1 |
9,6,2,4 |
2 | | Trivial (2 blocks) | 7-lug-2017 | | 2 |
10,6,2,4 |
2 | - Invers(10,04,02,06) | Trivial (2 blocks) | 7-lug-2017 | | 2 |
11,6,2,4 |
2 | - Invers(11,05,03,07) | Trivial (2 blocks) | 7-lug-2017 | | 2 |
12,6,2,4 |
2 | - Invers(12,06,04,08) | Trivial (2 blocks) | 7-lug-2017 | | 2 |
13,6,2,4 |
2 | - Invers(13,07,05,09) | Trivial (2 blocks) | 7-lug-2017 | | 2 |
14,6,2,4 |
3 | - Invers(14,08,06,10) | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 3 |
15,6,2,4 |
3 | - Invers(15,09,07,11) | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 3 |
16,6,2,4 |
3 | - Invers(16,10,08,12) | Trivial (3 blocks) | 7-lug-2017 | | 3 |
17,6,2,4 |
3 | - Invers(17,11,09,13) | Trivial (3 blocks) | 7-lug-2017 | | 3 |
18,6,2,4 |
3 | - Invers(18,12,10,14) | Trivial (3 blocks) | 7-lug-2017 | | 3 |
19,6,2,4 |
5 | - Invers(19,13,11,15) | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 5 |
20,6,2,4 |
5 | - Invers(20,14,12,16) | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 5 |
21,6,2,4 |
5 | - Invers(21,15,13,17) | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 5 |
22,6,2,4 |
6 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 5 |
23,6,2,4 |
7 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 6 |
24,6,2,4 |
7 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 6 |
25,6,2,4 |
8 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 7 |
26,6,2,4 |
9 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 7 |
27,6,2,4 |
9 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 8 |
28,6,2,4 |
10 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 8 |
29,6,2,4 |
11 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 9 |
30,6,2,4 |
12 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 9 |
31,6,2,4 |
13 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 10 |
32,6,2,4 |
13 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 11 |
33,6,2,4 |
14 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 11 |
34,6,2,4 |
15 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 12 |
35,6,2,4 |
16 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 13 |
36,6,2,4 |
17 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 14 |
37,6,2,4 |
17 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 14 |
38,6,2,4 |
18 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 15 |
39,6,2,4 |
20 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 16 |
40,6,2,4 |
20 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 17 |
41,6,2,4 |
21 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 18 |
42,6,2,4 |
21 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 19 |
43,6,2,4 |
24 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 20 |
44,6,2,4 |
24 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 21 |
45,6,2,4 |
26 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 21 |
46,6,2,4 |
26 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 22 |
47,6,2,4 |
29 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 23 |
48,6,2,4 |
29 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 24 |
49,6,2,4 |
31 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 26 |
50,6,2,4 |
31 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 27 |
51,6,2,4 |
34 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 28 |
52,6,2,4 |
34 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 29 |
53,6,2,4 |
36 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 30 |
54,6,2,4 |
36 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 31 |
55,6,2,4 |
39 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 32 |
56,6,2,4 |
40 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 33 |
57,6,2,4 |
41 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 35 |
58,6,2,4 |
43 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 36 |
59,6,2,4 |
45 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 37 |
60,6,2,4 |
46 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 38 |
61,6,2,4 |
47 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 40 |
62,6,2,4 |
48 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 41 |
63,6,2,4 |
50 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 42 |
64,6,2,4 |
52 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 44 |
65,6,2,4 |
53 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 45 |
66,6,2,4 |
55 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 47 |
67,6,2,4 |
55 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 48 |
68,6,2,4 |
58 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 50 |
69,6,2,4 |
59 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 51 |
70,6,2,4 |
60 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 53 |
71,6,2,4 |
62 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 54 |
72,6,2,4 |
64 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 56 |
73,6,2,4 |
65 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 57 |
74,6,2,4 |
66 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 59 |
75,6,2,4 |
67 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 60 |
76,6,2,4 |
69 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 62 |
77,6,2,4 |
71 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 64 |
78,6,2,4 |
72 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 65 |
79,6,2,4 |
74 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 67 |
80,6,2,4 |
74 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 69 |
81,6,2,4 |
77 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 71 |
82,6,2,4 |
78 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 72 |
83,6,2,4 |
79 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 74 |
84,6,2,4 |
81 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 76 |
85,6,2,4 |
83 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 78 |
86,6,2,4 |
84 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 80 |
87,6,2,4 |
85 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 82 |
88,6,2,4 |
86 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 84 |
89,6,2,4 |
89 | | already known design - Rebuilt by LDDr | 16-mag-2018 | Sum (v1+v2,k,t,m1+m2-1 | 86 |
90,6,2,4 |
90 | | Alessandro Jurcovich | 8-giu-2018 | reproposed | 87 |