REBUILT LIST 03

The following is a list of 105 coverings uploaded on June,9th, 2018. They have the same bound (B) of the old entries on Weef's site (now unavailable)

At the moment of the upload the old bound was not improved yet and and the new files has reconstructed using the same bound of the old registration. Methods used for these constructions is probably different by that one used by the first authors.

The method used for each construction is shown in the "note" field at the right of the table.

For further informations you can ask a specific question entering the Forum: wheels.forumcommunity.net (threads "Sito primati - Repository site" or "Registro Record in questo FORUM", "", or public board of teh same forum )

Entries
v,k,t,m	New b	Old b	Author	Date	note
12,2,2,3	30	30	already known design - Rebuilt by B-G	09-giu-18
13,2,2,3	36	36	already known design - Rebuilt by B-G	09-giu-18
13,2,2,4	22	22	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
14,2,2,3	42	42	already known design - Rebuilt by B-G	09-giu-18
14,2,2,4	26	26	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
14,3,3,5	70	70	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
15,2,2,3	49	49	already known design - Rebuilt by B-G	09-giu-18
15,2,2,4	30	30	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
15,3,3,6	50	50	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
16,2,2,3	56	56	already known design - Rebuilt by B-G	09-giu-18
16,2,2,4	35	35	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
16,3,3,5	112	112	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
16,3,3,6	65	65	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
16,3,3,7	39	39	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
17,2,2,3	64	64	already known design - Rebuilt by B-G	09-giu-18
17,2,2,4	40	40	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
17,3,3,6	80	80	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
17,3,3,7	49	49	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
17,8,7,13	6	6	already known design - Rebuilt by B-G	09-giu-18
17,9,3,4	6	6	already known design - Rebuilt by B-G	09-giu-18
18,2,2,3	72	72	already known design - Rebuilt by B-G	09-giu-18
18,2,2,4	45	45	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
18,3,3,5	168	168	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
18,3,3,6	98	98	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
18,9,3,4	6	6	already known design - Rebuilt by B-G	09-giu-18
18,9,8,14	6	6	already known design - Rebuilt by B-G	09-giu-18
19,2,2,3	81	81	already known design - Rebuilt by B-G	09-giu-18
19,2,2,4	51	51	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
19,3,3,6	119	119	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
19,3,3,7	72	72	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
19,9,3,4	8	8	already known design - Rebuilt by B-G	09-giu-18
19,10,9,15	8	8	already known design - Rebuilt by B-G	09-giu-18
20,2,2,3	90	90	already known design - Rebuilt by B-G	09-giu-18
20,2,2,4	57	57	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
20,3,3,5	240	240	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
20,3,3,6	140	140	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
20,3,3,7	87	87	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
20,9,3,4	9	9	already known design - Rebuilt by B-G	09-giu-18
21,2,2,3	100	100	already known design - Rebuilt by B-G	09-giu-18
21,2,2,4	63	63	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
21,3,3,6	168	168	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
21,3,3,7	105	105	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
21,9,3,4	11	11	already known design - Rebuilt by B-G	09-giu-18
22,2,2,3	110	110	already known design - Rebuilt by B-G	09-giu-18
22,2,2,4	70	70	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
22,3,3,5	330	330	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
22,3,3,7	124	124	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
22,3,3,10	41	41	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
22,9,3,4	13	13	already known design - Rebuilt by B-G	09-giu-18
23,2,2,3	121	121	already known design - Rebuilt by B-G	09-giu-18
23,2,2,4	77	77	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
23,3,3,6	228	228	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
23,3,3,7	145	145	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
23,9,3,4	15	15	already known design - Rebuilt by B-G	09-giu-18
24,2,2,3	132	132	already known design - Rebuilt by B-G	09-giu-18
24,2,2,4	84	84	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
24,3,3,5	440	440	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
24,3,3,6	264	264	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
24,9,3,4	17	17	already known design - Rebuilt by B-G	09-giu-18
25,2,2,3	144	144	already known design - Rebuilt by B-G	09-giu-18
25,2,2,4	92	92	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
25,3,3,5	506	506	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
25,3,3,6	300	300	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
25,3,3,7	192	192	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
25,9,3,4	20	20	already known design - Rebuilt by B-G	09-giu-18
26,2,2,3	156	156	already known design - Rebuilt by B-G	09-giu-18
26,2,2,4	100	100	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
26,3,3,5	572	572	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
26,3,3,6	345	345	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
26,3,3,7	220	220	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
26,9,3,4	23	23	already known design - Rebuilt by B-G	09-giu-18
27,2,2,3	169	169	already known design - Rebuilt by B-G	09-giu-18
27,2,2,4	108	108	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
27,3,3,5	650	650	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
27,3,3,6	390	390	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
27,3,3,7	252	252	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
28,2,2,3	182	182	already known design - Rebuilt by B-G	09-giu-18
28,2,2,4	117	117	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
28,3,3,5	728	728	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
28,3,3,6	440	440	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
28,3,3,7	284	284	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
28,6,4,8	93	93	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
29,2,2,3	196	196	already known design - Rebuilt by B-G	09-giu-18
29,2,2,4	126	126	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
29,3,3,5	819	819	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
29,3,3,6	495	495	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
29,3,3,7	320	320	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
29,10,7,15	37	37	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
30,2,2,3	210	210	already known design - Rebuilt by B-G	09-giu-18
30,2,2,4	135	135	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
30,3,3,5	910	910	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
30,3,3,6	550	550	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
31,2,2,3	225	225	already known design - Rebuilt by B-G	09-giu-18
31,2,2,4	145	145	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
31,3,3,5	1015	1015	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
31,3,3,6	616	616	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
31,3,3,7	400	400	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
31,3,3,8	280	280	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
32,2,2,3	240	240	already known design - Rebuilt by B-G	09-giu-18
32,2,2,4	155	155	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
32,3,3,5	1120	1120	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
32,3,3,6	682	682	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
32,3,3,7	445	445	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
32,3,3,8	312	312	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
32,5,3,6	86	86	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
32,9,4,8	29	29	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
32,10,5,10	36	36	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
33,2,2,3	256	256	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
33,2,2,4	165	165	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
33,3,3,5	1240	1240	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
33,3,3,6	754	754	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
33,3,3,7	495	495	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
34,2,2,3	272	272	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
34,2,2,4	176	176	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
34,3,3,5	1360	1360	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
34,3,3,6	832	832	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
34,7,4,9	72	72	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
34,9,4,8	39	39	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
35,2,2,3	289	289	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
35,2,2,4	187	187	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
35,3,3,5	1496	1496	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
35,3,3,6	910	910	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
36,2,2,3	306	306	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
36,2,2,4	198	198	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
36,3,3,5	1632	1632	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
36,3,3,6	1001	1001	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
36,5,3,6	120	120	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
36,7,4,9	92	92	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
36,9,4,8	47	47	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
37,2,2,3	324	324	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
37,2,2,4	210	210	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
37,3,3,5	1785	1785	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
37,3,3,6	1092	1092	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
38,2,2,3	342	342	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
38,2,2,4	222	222	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
38,3,3,5	1938	1938	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
38,3,3,6	1190	1190	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
39,2,2,3	361	361	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
39,2,2,4	234	234	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
39,3,3,5	2109	2109	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
39,3,3,6	1295	1295	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
39,3,3,7	858	858	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
40,2,2,3	380	380	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
40,2,2,4	247	247	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
40,3,3,5	2280	2280	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
40,3,3,6	1400	1400	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
40,3,3,10	364	364	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
41,2,2,3	400	400	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
41,2,2,4	260	260	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
41,3,3,5	2470	2470	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
41,3,3,6	1520	1520	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
41,3,3,10	396	396	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
42,2,2,3	420	420	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
42,3,3,5	2660	2660	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
42,3,3,6	1640	1640	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
43,2,2,3	441	441	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
43,3,3,5	2870	2870	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
43,3,3,6	1768	1768	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
44,2,2,3	462	462	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
44,3,3,5	3080	3080	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
44,3,3,6	1904	1904	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
45,2,2,3	484	484	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
45,3,3,5	3311	3311	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
45,3,3,6	2040	2040	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
45,3,3,7	1365	1365	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
46,2,2,3	506	506	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
46,3,3,5	3542	3542	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
46,3,3,6	2193	2193	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
47,2,2,3	529	529	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
47,3,3,5	3795	3795	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
47,3,3,6	2346	2346	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
48,2,2,3	552	552	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
48,3,3,5	4048	4048	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
48,3,3,6	2508	2508	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
49,2,2,3	576	576	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
49,3,3,5	4324	4324	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
49,3,3,6	2679	2679	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
50,2,2,3	600	600	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
50,3,3,5	4600	4600	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
50,3,3,6	2850	2850	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
51,2,2,3	625	625	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
51,3,3,5	4900	4900	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
51,3,3,6	3040	3040	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
51,3,3,7	2040	2040	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
52,2,2,3	650	650	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
52,3,3,5	5200	5200	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
52,3,3,6	3230	3230	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
53,2,2,3	676	676	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
53,3,3,5	5525	5525	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
53,3,3,6	3430	3430	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
54,2,2,3	702	702	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
54,3,3,5	5850	5850	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
54,3,3,6	3640	3640	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
55,2,2,3	729	729	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
55,3,3,5	6201	6201	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
55,3,3,6	3850	3850	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
56,2,2,3	756	756	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
56,3,3,5	6552	6552	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
56,3,3,6	4081	4081	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
57,2,2,3	784	784	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
57,3,3,5	6930	6930	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
57,3,3,6	4312	4312	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
57,3,3,7	2907	2907	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
58,2,2,3	812	812	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
58,3,3,5	7308	7308	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
58,3,3,6	4554	4554	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
59,2,2,3	841	841	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
59,3,3,5	7714	7714	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
59,3,3,6	4807	4807	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
60,2,2,3	870	870	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
60,2,2,4	570	570	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
60,3,3,5	8120	8120	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
60,3,3,6	5060	5060	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
61,2,2,3	900	900	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
61,3,3,5	8555	8555	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
61,3,3,6	5336	5336	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
62,2,2,3	930	930	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
62,3,3,5	8990	8990	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
62,3,3,6	5612	5612	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
62,5,2,6	44	44	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
63,2,2,3	961	961	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
63,3,3,6	5900	5900	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
63,3,3,7	3990	3990	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
64,2,2,3	992	992	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
64,3,3,5	9920	9920	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
64,3,3,6	6200	6200	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
65,2,2,3	1024	1024	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
65,2,2,4	672	672	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
65,3,3,5	10416	10416	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
65,3,3,6	6500	6500	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
66,2,2,3	1056	1056	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
66,2,2,4	693	693	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
66,3,3,5	10912	10912	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
66,3,3,6	6825	6825	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
67,2,2,3	1089	1089	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
67,2,2,4	715	715	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
67,3,3,5	11440	11440	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
67,3,3,6	7150	7150	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
68,2,2,3	1122	1122	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
68,2,2,4	737	737	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
68,3,3,5	11968	11968	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
68,3,3,6	7488	7488	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
68,4,4,7	92752	92752	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
69,2,2,3	1156	1156	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
69,2,2,4	759	759	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
69,3,3,5	12529	12529	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
69,3,3,6	7839	7839	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
69,3,3,7	5313	5313	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
69,4,4,7	98736	98736	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
70,2,2,3	1190	1190	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
70,2,2,4	782	782	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
70,3,3,5	13090	13090	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
70,3,3,6	8190	8190	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
70,4,4,7	104720	104720	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
71,3,3,5	13685	13685	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
71,3,3,6	8568	8568	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
71,4,4,7	111265	111265	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
72,3,3,5	14280	14280	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
72,3,3,6	8946	8946	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
72,4,4,7	117810	117810	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
72,5,2,6	58	58	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
73,3,3,5	14910	14910	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
73,3,3,6	9338	9338	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
73,4,4,7	124950	124950	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
74,3,3,5	15540	15540	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
74,3,3,6	9744	9744	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
74,4,4,7	132090	132090	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
74,5,2,6	61	61	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
74,6,4,12	1350	1350	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
74,7,2,4	50	50	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
75,3,3,5	16206	16206	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
75,3,3,6	10150	10150	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
75,3,3,7	6900	6900	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
75,4,4,7	139860	139860	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
76,3,3,5	16872	16872	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
76,3,3,6	10585	10585	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
76,4,4,7	147630	147630	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
76,6,4,12	1548	1548	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
76,7,2,4	52	52	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
77,3,3,5	17575	17575	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
77,3,3,6	11020	11020	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
77,4,4,7	156066	156066	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
78,3,3,5	18278	18278	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
78,3,3,6	11470	11470	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
78,4,4,7	164502	164502	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
79,3,3,5	19019	19019	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
79,3,3,6	11935	11935	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
79,4,4,7	173641	173641	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
79,7,2,4	57	57	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
80,3,3,5	19760	19760	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
80,3,3,6	12400	12400	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
80,4,4,7	182780	182780	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
80,7,2,4	58	58	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
81,3,3,5	20540	20540	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
81,3,3,6	12896	12896	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
81,3,3,7	8775	8775	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
81,4,4,7	192660	192660	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
81,7,2,4	59	59	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
82,3,3,5	21320	21320	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
82,3,3,6	13392	13392	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
82,4,4,7	202540	202540	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
82,7,2,4	61	61	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
83,3,3,5	22140	22140	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
83,3,3,6	13904	13904	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
83,4,4,7	213200	213200	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
83,7,2,4	62	62	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
84,3,3,5	22960	22960	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
84,3,3,6	14432	14432	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
84,4,4,7	223860	223860	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
84,7,2,4	64	64	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
84,8,3,6	385	385	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
85,3,3,5	23821	23821	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
85,3,3,6	14960	14960	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
85,4,4,7	235340	235340	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
85,7,2,4	65	65	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
86,3,3,5	24682	24682	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
86,3,3,6	15521	15521	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
86,4,4,7	246820	246820	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
86,7,2,4	67	67	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
87,2,2,3	1849	1849	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
87,3,3,5	25585	25585	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
87,3,3,6	16082	16082	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
87,3,3,7	10962	10962	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
87,4,4,7	259161	259161	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
87,5,2,4	127	127	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
87,8,3,6	428	428	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
88,2,2,3	1892	1892	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
88,3,3,5	26488	26488	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
88,3,3,6	16660	16660	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
88,4,4,7	271502	271502	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
88,7,2,4	70	70	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
89,2,2,3	1936	1936	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
89,3,3,5	27434	27434	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
89,3,3,6	17255	17255	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
89,4,4,7	284746	284746	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
89,7,2,4	71	71	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
89,8,3,6	456	456	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
90,3,3,5	28380	28380	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
90,3,3,6	17850	17850	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
90,4,4,7	297990	297990	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)
90,8,3,6	470	470	already known design - Rebuilt by LDDr	09-giu-18	Sum (v1+v2,k,t,m1+m2-1)